#include "ddr_common.h"

#define DDR_CLK_FLOATING
#define SW_WRDQLVL_EN

#define DDR_SIZE_TO_UBOOT		0xE602B000

#define CANDS_CTL_REG_BASE0 	0Xc0000000
#define CANDS_PI_REG_BASE0   	0Xc0000800
#define CANDS_PHY_REG_BASE0 	0Xc0002000

#define CANDS_CTL_REG_BASE1 	0Xc0800000
#define CANDS_PI_REG_BASE1   	0Xc0800800
#define CANDS_PHY_REG_BASE1 	0Xc0802000

#define CTL_REG_NUM				481
#define PI_REG_NUM				249
#define PHY_REG_NUM			1108
#define DDR0_SLEEP_WAIT_CNT 0x32
#define PUB0_TOP_PUB0_DUMMY_REG0 0xC00180BC
#define PUB0_APB_DFS_WR_MCTL_REG_CFG0 0x30010200
#define PUB_FC_CTRL 0x402E01E0
#define BUSMON_CFG 0x30010004
#define PUB0_APB_DFS_WR_MCTL_REG_CFG2 0x30010208
#define PUB0_APB_DFS_WR_MCTL_REG0_ADDR 0x30010210
#define PUB0_APB_DFS_WR_MCTL_REG0_DATA_F0 0x30010300
#define PUB0_APB_DFS_WR_MCTL_REG0_DATA_F1 0x30010380
#define PUB0_APB_DFS_WR_MCTL_REG0_DATA_F2 0x30010400
#define PUB0_APB_DFS_WR_MCTL_REG0_DATA_F3 0x30010480
#define PUB0_APB_DFS_WR_MCTL_REG1_ADDR 0x30010214
#define PUB0_APB_DFS_WR_MCTL_REG1_DATA_F0 0x30010304
#define PUB0_APB_DFS_WR_MCTL_REG1_DATA_F1 0x30010384
#define PUB0_APB_DFS_WR_MCTL_REG1_DATA_F2 0x30010404
#define PUB0_APB_DFS_WR_MCTL_REG1_DATA_F3 0x30010484
#define PUB0_APB_DFS_WR_MCTL_REG2_ADDR 0x30010218
#define PUB0_APB_DFS_WR_MCTL_REG2_DATA_F0 0x30010308
#define PUB0_APB_DFS_WR_MCTL_REG2_DATA_F1 0x30010388
#define PUB0_APB_DFS_WR_MCTL_REG2_DATA_F2 0x30010408
#define PUB0_APB_DFS_WR_MCTL_REG2_DATA_F3 0x30010488
#define PUB0_APB_DFS_WR_MCTL_REG3_ADDR 0x3001021c
#define PUB0_APB_DFS_WR_MCTL_REG3_DATA_F0 0x3001030c
#define PUB0_APB_DFS_WR_MCTL_REG3_DATA_F1 0x3001038c
#define PUB0_APB_DFS_WR_MCTL_REG3_DATA_F2 0x3001040c
#define PUB0_APB_DFS_WR_MCTL_REG3_DATA_F3 0x3001048c
#define PUB0_APB_DFS_WR_MCTL_REG4_ADDR 0x30010220
#define PUB0_APB_DFS_WR_MCTL_REG4_DATA_F0 0x30010310
#define PUB0_APB_DFS_WR_MCTL_REG4_DATA_F1 0x30010390
#define PUB0_APB_DFS_WR_MCTL_REG4_DATA_F2 0x30010410
#define PUB0_APB_DFS_WR_MCTL_REG4_DATA_F3 0x30010490
#define PUB0_APB_DFS_WR_MCTL_REG5_ADDR 0x30010224
#define PUB0_APB_DFS_WR_MCTL_REG5_DATA_F0 0x30010314
#define PUB0_APB_DFS_WR_MCTL_REG5_DATA_F1 0x30010394
#define PUB0_APB_DFS_WR_MCTL_REG5_DATA_F2 0x30010414
#define PUB0_APB_DFS_WR_MCTL_REG5_DATA_F3 0x30010494
#define PUB0_APB_DFS_WR_MCTL_REG6_ADDR 0x30010228
#define PUB0_APB_DFS_WR_MCTL_REG6_DATA_F0 0x30010318
#define PUB0_APB_DFS_WR_MCTL_REG6_DATA_F1 0x30010398
#define PUB0_APB_DFS_WR_MCTL_REG6_DATA_F2 0x30010418
#define PUB0_APB_DFS_WR_MCTL_REG6_DATA_F3 0x30010498
#define PUB0_APB_DFS_WR_MCTL_REG7_ADDR 0x3001022c
#define PUB0_APB_DFS_WR_MCTL_REG7_DATA_F0 0x3001031c
#define PUB0_APB_DFS_WR_MCTL_REG7_DATA_F1 0x3001039c
#define PUB0_APB_DFS_WR_MCTL_REG7_DATA_F2 0x3001041c
#define PUB0_APB_DFS_WR_MCTL_REG7_DATA_F3 0x3001049c
#define PUB0_APB_DFS_WR_MCTL_REG8_ADDR 0x30010230
#define PUB0_APB_DFS_WR_MCTL_REG8_DATA_F0 0x30010320
#define PUB0_APB_DFS_WR_MCTL_REG8_DATA_F1 0x300103a0
#define PUB0_APB_DFS_WR_MCTL_REG8_DATA_F2 0x30010420
#define PUB0_APB_DFS_WR_MCTL_REG8_DATA_F3 0x300104a0
#define PUB0_APB_DFS_WR_MCTL_REG9_ADDR 0x30010234
#define PUB0_APB_DFS_WR_MCTL_REG9_DATA_F0 0x30010324
#define PUB0_APB_DFS_WR_MCTL_REG9_DATA_F1 0x300103a4
#define PUB0_APB_DFS_WR_MCTL_REG9_DATA_F2 0x30010424
#define PUB0_APB_DFS_WR_MCTL_REG9_DATA_F3 0x300104a4
#define PUB0_APB_DFS_WR_MCTL_REG10_ADDR 0x30010238
#define PUB0_APB_DFS_WR_MCTL_REG10_DATA_F0 0x30010328
#define PUB0_APB_DFS_WR_MCTL_REG10_DATA_F1 0x300103a8
#define PUB0_APB_DFS_WR_MCTL_REG10_DATA_F2 0x30010428
#define PUB0_APB_DFS_WR_MCTL_REG10_DATA_F3 0x300104a8
#define PUB0_APB_DFS_WR_MCTL_REG11_ADDR 0x3001023c
#define PUB0_APB_DFS_WR_MCTL_REG11_DATA_F0 0x3001032c
#define PUB0_APB_DFS_WR_MCTL_REG11_DATA_F1 0x300103ac
#define PUB0_APB_DFS_WR_MCTL_REG11_DATA_F2 0x3001042c
#define PUB0_APB_DFS_WR_MCTL_REG11_DATA_F3 0x300104ac
#define PUB0_APB_DFS_WR_MCTL_REG12_ADDR 0x30010240
#define PUB0_APB_DFS_WR_MCTL_REG12_DATA_F0 0x30010330
#define PUB0_APB_DFS_WR_MCTL_REG12_DATA_F1 0x300103b0
#define PUB0_APB_DFS_WR_MCTL_REG12_DATA_F2 0x30010430
#define PUB0_APB_DFS_WR_MCTL_REG12_DATA_F3 0x300104b0
#define PUB0_APB_DFS_WR_MCTL_REG13_ADDR 0x30010244
#define PUB0_APB_DFS_WR_MCTL_REG13_DATA_F0 0x30010334
#define PUB0_APB_DFS_WR_MCTL_REG13_DATA_F1 0x300103b4
#define PUB0_APB_DFS_WR_MCTL_REG13_DATA_F2 0x30010434
#define PUB0_APB_DFS_WR_MCTL_REG13_DATA_F3 0x300104b4
#define PUB0_APB_DFS_WR_MCTL_REG14_ADDR 0x30010248
#define PUB0_APB_DFS_WR_MCTL_REG14_DATA_F0 0x30010338
#define PUB0_APB_DFS_WR_MCTL_REG14_DATA_F1 0x300103b8
#define PUB0_APB_DFS_WR_MCTL_REG14_DATA_F2 0x30010438
#define PUB0_APB_DFS_WR_MCTL_REG14_DATA_F3 0x300104b8
#define PUB0_APB_DFS_WR_MCTL_REG15_ADDR 0x3001024c
#define PUB0_APB_DFS_WR_MCTL_REG15_DATA_F0 0x3001033c
#define PUB0_APB_DFS_WR_MCTL_REG15_DATA_F1 0x300103bc
#define PUB0_APB_DFS_WR_MCTL_REG15_DATA_F2 0x3001043c
#define PUB0_APB_DFS_WR_MCTL_REG15_DATA_F3 0x300104bc
#define PUB0_APB_DFS_WR_MCTL_REG16_ADDR 0x30010250
#define PUB0_APB_DFS_WR_MCTL_REG16_DATA_F0 0x30010340
#define PUB0_APB_DFS_WR_MCTL_REG16_DATA_F1 0x300103c0
#define PUB0_APB_DFS_WR_MCTL_REG16_DATA_F2 0x30010440
#define PUB0_APB_DFS_WR_MCTL_REG16_DATA_F3 0x300104c0
#define PUB0_APB_DFS_WR_MCTL_REG17_ADDR 0x30010254
#define PUB0_APB_DFS_WR_MCTL_REG17_DATA_F0 0x30010344
#define PUB0_APB_DFS_WR_MCTL_REG17_DATA_F1 0x300103c4
#define PUB0_APB_DFS_WR_MCTL_REG17_DATA_F2 0x30010444
#define PUB0_APB_DFS_WR_MCTL_REG17_DATA_F3 0x300104c4
#define PUB0_APB_DFS_WR_MCTL_REG18_ADDR 0x30010258
#define PUB0_APB_DFS_WR_MCTL_REG18_DATA_F0 0x30010348
#define PUB0_APB_DFS_WR_MCTL_REG18_DATA_F1 0x300103c8
#define PUB0_APB_DFS_WR_MCTL_REG18_DATA_F2 0x30010448
#define PUB0_APB_DFS_WR_MCTL_REG18_DATA_F3 0x300104c8
#define PUB0_APB_DFS_WR_MCTL_REG19_ADDR 0x3001025c
#define PUB0_APB_DFS_WR_MCTL_REG19_DATA_F0 0x3001034c
#define PUB0_APB_DFS_WR_MCTL_REG19_DATA_F1 0x300103cc
#define PUB0_APB_DFS_WR_MCTL_REG19_DATA_F2 0x3001044c
#define PUB0_APB_DFS_WR_MCTL_REG19_DATA_F3 0x300104cc

#define	CANDS_CTL0_(x)	    (CANDS_CTL_REG_BASE0+4*(x))
#define	CANDS_PHY0_(x)	    (CANDS_PHY_REG_BASE0+4*(x))
#define	CANDS_PI0_(x)       (CANDS_PI_REG_BASE0+4*(x))

#define	CANDS_CTL1_(x)	    (CANDS_CTL_REG_BASE1+4*(x))
#define	CANDS_PHY1_(x)	    (CANDS_PHY_REG_BASE1+4*(x))
#define	CANDS_PI1_(x)	    (CANDS_PI_REG_BASE1+4*(x))

#define CGM_AON_PUB_APB_CFG     0XE42D0328

#define PMU_DUMMY_REG		0XE42E0098
#define ANA_DPLL_THM_TOP_0_CLK_CTRL_0	0XE4106000
#define ANA_DPLL_THM_TOP_0_MODU_CTRL_0	0XE4106004
#define ANA_DPLL_THM_TOP_0_DIV_CTRL_0	0XE4106008
#define ANA_DPLL_THM_TOP_0_PWR_CTRL_0	0XE410600C
#define ANA_DPLL_THM_TOP_0_REG_SEL_CFG_0	0XE4106020

#define ANA_DPLL_THM_TOP_1_CLK_CTRL_0	0XE410c000
#define ANA_DPLL_THM_TOP_1_MODU_CTRL_0	0XE410c004
#define ANA_DPLL_THM_TOP_1_DIV_CTRL_0	0XE410c008
#define ANA_DPLL_THM_TOP_1_PWR_CTRL_0	0XE410c00C
#define ANA_DPLL_THM_TOP_1_REG_SEL_CFG_0	0XE410c020

#define BW_MB(x) (x*1024*1024)
#define BW_KB(x) (x*1024)
#define BW_B(x)  (x)
#define TIME_MS_MAX 165356
#define DFS_TIMER_STEP 38.5

#define BUS_MONITOR_TIMER_BASE	0X404D0000
#define BUS_MONITOR_TIMER_CTRL	(BUS_MONITOR_TIMER_BASE+0x0)
#define BUS_MONITOR_TIMER_HIGH_LEN_T1	(BUS_MONITOR_TIMER_BASE+0x4)
#define BUS_MONITOR_TIMER_LOW_LEN_T1	(BUS_MONITOR_TIMER_BASE+0x8)
#define BUS_MONITOR_TIMER_COUNT_NUM_T1	(BUS_MONITOR_TIMER_BASE+0xc)
#define BUS_MONITOR_TIMER_HIGH_LEN_T2	(BUS_MONITOR_TIMER_BASE+0x10)
#define BUS_MONITOR_TIMER_LOW_LEN_T2	(BUS_MONITOR_TIMER_BASE+0x14)
#define BUS_MONITOR_TIMER_COUNT_NUM_T2	(BUS_MONITOR_TIMER_BASE+0x18)
#define BUS_MONITOR_TIMER_OUT_SEL	(BUS_MONITOR_TIMER_BASE+0x1c)

#define AON_APB_CGM_CFG		0XE42e0098
#define AON_APB_CGM_REG1	0X402e0138
#define AON_APB_CGM_CLK_TOP_REG1	0XE42e013c
#define AON_APB_PUB_CTRL		0XE42E01C0
#define AON_APB_PUB_FC_CTRL		0XE42E01e0
#define AON_APB_EMC_CKG_SEL		0XE42E01E4

#define PMU_APB_PD_PUB0_SYS_CFG		0XE42B0044
#define PMU_APB_PD_PUB1_SYS_CFG		0XE42B005C
#define PMU_APB_DDR_SLEEP_CTRL		0XE42c0008
#define PMU_APB_FENCING_LOCK_BYP	0XE42C00D0

#define PMU_APB_DDR0_CHN_SLEEP_CTRL0   0X402B00F4
#define PMU_APB_DDR1_CHN_SLEEP_CTRL0   0X402B00F8


#define AON_APB_EB_AON_ADD1	0X402e01d0
#define AON_CLK_PREDIV_GATE_EN_SEL3_CFG		0X402D0048
#define AON_CLK_PREDIV_GATE_EN_CTL3_CFG		0X402D005C

//#define PUB0_APB_FREQ_CHANGE_LP4_INIT	0X300101E0
//#define PUB1_APB_FREQ_CHANGE_LP4_INIT	0X308101E0
//#define PUB0_APB_FREQ_ACK_LP4_INIT	0X300111E0
//#define PUB1_APB_FREQ_ACK_LP4_INIT	0X308111E0
//#define PUB0_APB_FREQ_CHANGE_WCL_LP4_INIT	0X300121E0
//#define PUB1_APB_FREQ_CHANGE_WCL_LP4_INIT	0X308121E0

#define PUB0_APB_FREQ_CHANGE_LP4_REQ	0xc001005c
#define PUB0_APB_FREQ_CHANGE_LP4_ACK	0xc00180bc
#define PUB0_APB_FREQ_CHANGE_LP4_TYPE	0xc001005c
#define PUB1_APB_FREQ_CHANGE_LP4_REQ	0xc081005c
#define PUB1_APB_FREQ_CHANGE_LP4_ACK	0xc08180a0
#define PUB1_APB_FREQ_CHANGE_LP4_TYPE	0xc081005c

#define PUB0_APB_PUT_INT	0X30010000
#define PUB0_APB_BUS_MON	0X30010004
#define PUB0_APB_DMC_PORTS_MPU_EN		0X3001000C
#define PUB0_APB_DMC_PORT0_MPU_RANGE	0X3001003C
#define PUB0_APB_DMC_PORT1_MPU_RANGE	0X30010040
#define PUB0_APB_DMC_PORT2_MPU_RANGE	0X30010044
#define PUB0_APB_DMC_PORT3_MPU_RANGE	0X30010048
#define PUB0_APB_DMC_PORT4_MPU_RANGE	0X3001004C
#define PUB0_APB_DMC_PORT5_MPU_RANGE	0X30010050
#define PUB0_APB_DMC_PORT6_MPU_RANGE	0X30010054
#define PUB0_APB_DMC_PORT7_MPU_RANGE	0X30010058
#define PUB0_APB_DMC_PORT8_MPU_RANGE	0X3001005C
#define PUB0_APB_DMC_PORT9_MPU_RANGE	0X30010060
#define PUB0_APB_DMC_PORT10_MPU_RANGE	0X30010064

#define PUB0_APB_DMC_PORT0_DUMP_ADDR	0X30010068
#define PUB0_APB_DMC_PORT1_DUMP_RANGE	0X3001006C
#define PUB0_APB_DMC_PORT2_DUMP_RANGE	0X30010070
#define PUB0_APB_DMC_PORT3_DUMP_RANGE	0X30010074
#define PUB0_APB_DMC_PORT4_DUMP_RANGE	0X30010078
#define PUB0_APB_DMC_PORT5_DUMP_RANGE	0X3001007C
#define PUB0_APB_DMC_PORT6_DUMP_RANGE	0X30010080
#define PUB0_APB_DMC_PORT7_DUMP_RANGE	0X30010084
#define PUB0_APB_DMC_PORT8_DUMP_RANGE	0X30010088
#define PUB0_APB_DMC_PORT9_DUMP_RANGE	0X3001008C
#define PUB0_APB_DMC_PORT10_DUMP_RANGE	0X30010090


#define PUB0_APB_DFS_WR_MCTL_REG_CFG0	0x30010200
#define PUB0_APB_DFS_WR_MCTL_REG_CFG2	0x30010208
#define PUB0_APB_DFS_WR_MCTL_REG0_ADDR	0x30010210
#define PUB0_APB_DFS_WR_MCTL_REG1_ADDR	0x30010214
#define PUB0_APB_DFS_WR_MCTL_REG2_ADDR	0x30010218
#define PUB0_APB_DFS_WR_MCTL_REG3_ADDR	0x3001021c
#define PUB0_APB_DFS_WR_MCTL_REG4_ADDR	0x30010220
#define PUB0_APB_DFS_WR_MCTL_REG5_ADDR	0x30010224

#define PUB0_APB_DFS_WR_MCTL_REG0_DATA_F0	0x30010300
#define PUB0_APB_DFS_WR_MCTL_REG0_DATA_F1	0x30010380
#define PUB0_APB_DFS_WR_MCTL_REG0_DATA_F2	0x30010400
#define PUB0_APB_DFS_WR_MCTL_REG0_DATA_F3	0x30010480


#define PUB0_APB_DFS_WR_MCTL_REG1_DATA_F0	0x30010304
#define PUB0_APB_DFS_WR_MCTL_REG1_DATA_F1	0x30010384
#define PUB0_APB_DFS_WR_MCTL_REG1_DATA_F2	0x30010404
#define PUB0_APB_DFS_WR_MCTL_REG1_DATA_F3	0x30010484


#define PUB0_APB_DMC_PORTS_MPU_SEL		0X300100A0

#define PUB0_APB_PUB_CHN0_LP_CTRL               0Xc0014030
#define PUB0_APB_PUB_CHN1_LP_CTRL               0XC0014034
#define PUB0_APB_PUB_CHN2_LP_CTRL               0XC0014038
#define PUB0_APB_PUB_CHN3_LP_CTRL               0XC001403c
#define PUB0_APB_PUB_CHN4_LP_CTRL               0XC0014040
#define PUB0_APB_PUB_CHN5_LP_CTRL               0XC0014044
#define PUB0_APB_PUB_MTX_LP_CFG2                0XC00100C8


#define PUB1_APB_PUT_INT	0X30810000
#define PUB1_APB_BUS_MON	0X30810004
#define PUB1_APB_DMC_PORTS_MPU_EN		0X3081000C
#define PUB1_APB_DMC_PORT0_MPU_RANGE	0X3081003C
#define PUB1_APB_DMC_PORT1_MPU_RANGE	0X30810040
#define PUB1_APB_DMC_PORT2_MPU_RANGE	0X30810044
#define PUB1_APB_DMC_PORT3_MPU_RANGE	0X30810048
#define PUB1_APB_DMC_PORT4_MPU_RANGE	0X3081004C
#define PUB1_APB_DMC_PORT5_MPU_RANGE	0X30810050
#define PUB1_APB_DMC_PORT6_MPU_RANGE	0X30810054
#define PUB1_APB_DMC_PORT7_MPU_RANGE	0X30810058
#define PUB1_APB_DMC_PORT8_MPU_RANGE	0X3081005C
#define PUB1_APB_DMC_PORT9_MPU_RANGE	0X30810060
#define PUB1_APB_DMC_PORT10_MPU_RANGE	0X30810064

#define PUB1_APB_DMC_PORT0_DUMP_ADDR	0X30810068
#define PUB1_APB_DMC_PORT1_DUMP_RANGE	0X3081006C
#define PUB1_APB_DMC_PORT2_DUMP_RANGE	0X30810070
#define PUB1_APB_DMC_PORT3_DUMP_RANGE	0X30810074
#define PUB1_APB_DMC_PORT4_DUMP_RANGE	0X30810078
#define PUB1_APB_DMC_PORT5_DUMP_RANGE	0X3081007C
#define PUB1_APB_DMC_PORT6_DUMP_RANGE	0X30810080
#define PUB1_APB_DMC_PORT7_DUMP_RANGE	0X30810084
#define PUB1_APB_DMC_PORT8_DUMP_RANGE	0X30810088
#define PUB1_APB_DMC_PORT9_DUMP_RANGE	0X3081008C
#define PUB1_APB_DMC_PORT10_DUMP_RANGE	0X30810090

#define PUB1_APB_DMC_PORTS_MPU_SEL	0X308100A0

#define PUB1_APB_PUB_CHN0_LP_CTRL       0X30814058
#define PUB1_APB_PUB_CHN1_LP_CTRL       0X3081405C
#define PUB1_APB_PUB_CHN2_LP_CTRL       0X30814060
#define PUB1_APB_PUB_CHN3_LP_CTRL       0X30814064
#define PUB1_APB_PUB_CHN4_LP_CTRL       0X30814068
#define PUB1_APB_PUB_CHN5_LP_CTRL       0X3081406C
#define PUB1_APB_PUB_CHN6_LP_CTRL       0X30814070
#define PUB1_APB_PUB_CHN7_LP_CTRL       0X30814074
#define PUB1_APB_PUB_CHN8_LP_CTRL       0X30814078
#define PUB1_APB_PUB_CHN9_LP_CTRL       0X3081407C
#define PUB1_APB_PUB_CHN10_LP_CTRL      0X30814080



#if 0
#define BASE_BIST 0
#define BIST_CTRL                                 (BASE_BIST+0x0 )
#define BIST_TRANS_NUM                            (BASE_BIST+0x4 )
#define BIST_START_ADDRESS                        (BASE_BIST+0x8 )
#define BIST_DATA_MASK                            (BASE_BIST+0xC )
#define BIST_SIPI_DATA_00                         (BASE_BIST+0x10)
#define BIST_SIPI_DATA_01                         (BASE_BIST+0x14)
#define BIST_SIPI_DATA_02                         (BASE_BIST+0x18)
#define BIST_SIPI_DATA_03                         (BASE_BIST+0x1C)
#define BIST_SIPI_DATA_04                         (BASE_BIST+0x20)
#define BIST_SIPI_DATA_05                         (BASE_BIST+0x24)
#define BIST_SPIP_BIT_PATTERN_0                   (BASE_BIST+0x28)
#define BIST_SPIP_BIT_PATTERN_1                   (BASE_BIST+0x2C)
#define BIST_DATA_0_PATTERN                       (BASE_BIST+0x30)
#define BIST_DATA_1_PATTERN                       (BASE_BIST+0x34)
#define BIST_DATA_2_PATTERN                       (BASE_BIST+0x38)
#define BIST_DATA_3_PATTERN                       (BASE_BIST+0x3C)
#define BIST_DATA_4_PATTERN                       (BASE_BIST+0x40)
#define BIST_DATA_5_PATTERN                       (BASE_BIST+0x44)
#define BIST_DATA_6_PATTERN                       (BASE_BIST+0x48)
#define BIST_DATA_7_PATTERN                       (BASE_BIST+0x4C)
#define BIST_DATA_8_PATTERN                       (BASE_BIST+0x50)
#define BIST_DATA_9_PATTERN                       (BASE_BIST+0x54)
#define BIST_DATA_10_PATTERN                      (BASE_BIST+0x58)
#define BIST_DATA_11_PATTERN                      (BASE_BIST+0x5C)
#define BIST_DATA_12_PATTERN                      (BASE_BIST+0x60)
#define BIST_DATA_13_PATTERN                      (BASE_BIST+0x64)
#define BIST_DATA_14_PATTERN                      (BASE_BIST+0x68)
#define BIST_DATA_15_PATTERN                      (BASE_BIST+0x6C)
#define BIST_DATA_16_PATTERN                      (BASE_BIST+0x70)
#define BIST_DATA_17_PATTERN                      (BASE_BIST+0x74)
#define BIST_DATA_18_PATTERN                      (BASE_BIST+0x78)
#define BIST_DATA_19_PATTERN                      (BASE_BIST+0x7C)
#define BIST_DATA_20_PATTERN                      (BASE_BIST+0x80)
#define BIST_DATA_21_PATTERN                      (BASE_BIST+0x84)
#define BIST_DATA_22_PATTERN                      (BASE_BIST+0x88)
#define BIST_DATA_23_PATTERN                      (BASE_BIST+0x8C)
#define BIST_DATA_24_PATTERN                      (BASE_BIST+0x90)
#define BIST_DATA_25_PATTERN                      (BASE_BIST+0x94)
#define BIST_DATA_26_PATTERN                      (BASE_BIST+0x98)
#define BIST_DATA_27_PATTERN                      (BASE_BIST+0x9C)
#define BIST_DATA_28_PATTERN                      (BASE_BIST+0xA0)
#define BIST_DATA_29_PATTERN                      (BASE_BIST+0xA4)
#define BIST_DATA_30_PATTERN                      (BASE_BIST+0xA8)
#define BIST_DATA_31_PATTERN                      (BASE_BIST+0xAC)
#define BIST_STATUS                               (BASE_BIST+0xB0)
#define BIST_FAIL_ADDR                            (BASE_BIST+0xB4)
#define BIST_FAIL_DATA0                           (BASE_BIST+0xB8)
#define BIST_FAIL_DATA1                           (BASE_BIST+0xBC)
#define BIST_FAIL_DATA2                           (BASE_BIST+0xC0)
#define BIST_FAIL_DATA3                           (BASE_BIST+0xC4)
#define BIST_LFSR_SEED                            (BASE_BIST+0xC8)
#endif

#define DDR0_PHY_RET_CFG    0X402B0108
#define DDR1_PHY_RET_CFG    0X402B010C
#define SLEEP_CTRL          0X402B00E8
#define DDR_SLEEP_CTRL      0X402B00EC
#define PD_PUBCP_SYS_CFG    0X402B0084

#define PD_CA53_TOP_CFG     0X402B0000
#define PD_CA53_LIT_MP4_CFG 0X402B0004
#define PD_CA53_LIT_C0_CFG  0X402B000C
#define PD_CA53_LIT_C1_CFG  0X402B0010
#define PD_CA53_LIT_C2_CFG  0X402B0014
#define PD_CA53_LIT_C3_CFG  0X402B0018

#define PD_CA53_BIG_MP4_CFG 0X402B001C
#define PD_CA53_BIG_C0_CFG  0X402B0020
#define PD_CA53_BIG_C1_CFG  0X402B0024
#define PD_CA53_BIG_C2_CFG  0X402B0028
#define PD_CA53_BIG_C3_CFG  0X402B002C

#define SYS_SOFT_RST        0X402B00C4

#define DDR0_ACC_RDY       0XE42B02CC
#define DDR0_LIGHT_ACC_RDY		0XE42B02D0
#define DDR0_SLP_CFG			0XE42B02D4
#define DDR1_ACC_RDY       0XE42B02D8
#define AON_TOP_PUB0_SYS_SLEEP_CTRL     0XE42B012c
#define AON_TOP_PUB1_SYS_SLEEP_CTRL     0XE42B0130
#define DDR1_LIGHT_ACC_RDY		0XE42B02DC
#define DDR1_SLP_CFG			0XE42B02E0


#define PUB0_SOFT_DFS_CTRL 		0xc0018000
#define PUB0_HARD_DFS_CTRL_LO 	0x30018004
#define PUB0_HARD_DFS_CTRL_HI 	0x30018008
//#define PUB0_SOFT_DFS_CTRL 		0xc0018000
#define PUB0_BIST_TEST_CTRL 	0x30018028
#define PUB0_LP_GEN_CTRL 		0xc001802C
#define PUB0_PURE_SW_DFS_CTRL	0x30018030
#define PUB0_DFS_STATUS			0xc0018034

#define PUB1_SOFT_DFS_CTRL 		0xc0818000
#define PUB1_HARD_DFS_CTRL_LO 	0x30818004
#define PUB1_HARD_DFS_CTRL_HI 	0x30818008
//#define PUB1_SOFT_DFS_CTRL 		0xc0818000
#define PUB1_BIST_TEST_CTRL 	0x30818028
#define PUB1_LP_GEN_CTRL 		0x3081802C
#define PUB1_PURE_SW_DFS_CTRL	0x30818030
#define PUB1_DFS_STATUS			0x30818034

#define PUB0_APB_BUSMON_CFG 0x30010004
#define PUB1_APB_BUSMON_CFG 0x30810004

#define PUB0_DFS_BUSMON_BASE 0x300C0000
#define PUB1_DFS_BUSMON_BASE 0x308C0000

#define PUB0_DFS_BUSMON_CFG 		         (PUB0_DFS_BUSMON_BASE)
#define PUB0_DFS_BUSMON_INT_EN 		         (PUB0_DFS_BUSMON_BASE+0x4)
#define PUB0_DFS_BUSMON_INT_CLR 	         (PUB0_DFS_BUSMON_BASE+0x8)
#define PUB0_DFS_BUSMON_INT_STATUS           (PUB0_DFS_BUSMON_BASE+0xC)
#define PUB0_DFS_BUSMON_BDWIDTH_CNT_W0       (PUB0_DFS_BUSMON_BASE+0x10)
#define PUB0_DFS_BUSMON_BDWIDTH_CNT_W1       (PUB0_DFS_BUSMON_BASE+0x14)
#define PUB0_DFS_BUSMON_BDWIDTH_CNT_R0       (PUB0_DFS_BUSMON_BASE+0x18)
#define PUB0_DFS_BUSMON_BDWIDTH_CNT_R1       (PUB0_DFS_BUSMON_BASE+0x1C)

#define PUB0_DFS_BUSMON_OVERFLOW_TSHOLD_F0   (PUB0_DFS_BUSMON_BASE+0x20)
#define PUB0_DFS_BUSMON_UNDERFLOW_TSHOLD_F0  (PUB0_DFS_BUSMON_BASE+0x24)
#define PUB0_DFS_BUSMON_OVERFLOW_TSHOLD_F1   (PUB0_DFS_BUSMON_BASE+0x28)
#define PUB0_DFS_BUSMON_UNDERFLOW_TSHOLD_F1  (PUB0_DFS_BUSMON_BASE+0x2C)
#define PUB0_DFS_BUSMON_OVERFLOW_TSHOLD_F2   (PUB0_DFS_BUSMON_BASE+0x30)
#define PUB0_DFS_BUSMON_UNDERFLOW_TSHOLD_F2  (PUB0_DFS_BUSMON_BASE+0x34)
#define PUB0_DFS_BUSMON_OVERFLOW_TSHOLD_F3   (PUB0_DFS_BUSMON_BASE+0x38)
#define PUB0_DFS_BUSMON_UNDERFLOW_TSHOLD_F3  (PUB0_DFS_BUSMON_BASE+0x3C)
#define PUB0_DFS_BUSMON_BDWIDTH_BASE_NUM     (PUB0_DFS_BUSMON_BASE+0x40)


#define PUB1_DFS_BUSMON_CFG 				 (PUB1_DFS_BUSMON_BASE)
#define PUB1_DFS_BUSMON_INT_EN 				 (PUB1_DFS_BUSMON_BASE+0x4)
#define PUB1_DFS_BUSMON_INT_CLR 			 (PUB1_DFS_BUSMON_BASE+0x8)
#define PUB1_DFS_BUSMON_INT_STATUS  		 (PUB1_DFS_BUSMON_BASE+0xC)
#define PUB1_DFS_BUSMON_BDWIDTH_CNT_W0  	 (PUB1_DFS_BUSMON_BASE+0x10)
#define PUB1_DFS_BUSMON_BDWIDTH_CNT_W1  	 (PUB1_DFS_BUSMON_BASE+0x14)
#define PUB1_DFS_BUSMON_BDWIDTH_CNT_R0  	 (PUB1_DFS_BUSMON_BASE+0x18)
#define PUB1_DFS_BUSMON_BDWIDTH_CNT_R1  	 (PUB1_DFS_BUSMON_BASE+0x1C)

#define PUB1_DFS_BUSMON_OVERFLOW_TSHOLD_F0   (PUB1_DFS_BUSMON_BASE+0x20)
#define PUB1_DFS_BUSMON_UNDERFLOW_TSHOLD_F0  (PUB1_DFS_BUSMON_BASE+0x24)
#define PUB1_DFS_BUSMON_OVERFLOW_TSHOLD_F1   (PUB1_DFS_BUSMON_BASE+0x28)
#define PUB1_DFS_BUSMON_UNDERFLOW_TSHOLD_F1  (PUB1_DFS_BUSMON_BASE+0x2C)
#define PUB1_DFS_BUSMON_OVERFLOW_TSHOLD_F2   (PUB1_DFS_BUSMON_BASE+0x30)
#define PUB1_DFS_BUSMON_UNDERFLOW_TSHOLD_F2  (PUB1_DFS_BUSMON_BASE+0x34)
#define PUB1_DFS_BUSMON_OVERFLOW_TSHOLD_F3   (PUB1_DFS_BUSMON_BASE+0x38)
#define PUB1_DFS_BUSMON_UNDERFLOW_TSHOLD_F3  (PUB1_DFS_BUSMON_BASE+0x3C)
#define PUB1_DFS_BUSMON_BDWIDTH_BASE_NUM     (PUB1_DFS_BUSMON_BASE+0x40)


#define PUB0_AXI_BUSMON0_BASE 0x30020000
#define PUB0_AXI_BUSMON1_BASE 0x30030000
#define PUB0_AXI_BUSMON2_BASE 0x30040000
#define PUB0_AXI_BUSMON3_BASE 0x30050000
#define PUB0_AXI_BUSMON4_BASE 0x30060000
#define PUB0_AXI_BUSMON5_BASE 0x30070000
#define PUB0_AXI_BUSMON6_BASE 0x30080000
#define PUB0_AXI_BUSMON7_BASE 0x30090000
#define PUB0_AXI_BUSMON8_BASE 0x300A0000
#define PUB0_AXI_BUSMON9_BASE 0x300B0000
#define PUB0_AXI_BUSMON10_BASE 0x300F0000

#define PUB1_AXI_BUSMON0_BASE 0x30820000
#define PUB1_AXI_BUSMON1_BASE 0x30830000
#define PUB1_AXI_BUSMON2_BASE 0x30840000
#define PUB1_AXI_BUSMON3_BASE 0x30850000
#define PUB1_AXI_BUSMON4_BASE 0x30860000
#define PUB1_AXI_BUSMON5_BASE 0x30870000
#define PUB1_AXI_BUSMON6_BASE 0x30880000
#define PUB1_AXI_BUSMON7_BASE 0x30890000
#define PUB1_AXI_BUSMON8_BASE 0x308A0000
#define PUB1_AXI_BUSMON9_BASE 0x308B0000
#define PUB1_AXI_BUSMON10_BASE 0x308F0000

#define PUB0_AXI_BUSMON_CHN10_CFG 	   (PUB0_AXI_BUSMON10_BASE+0x0)
#define PUB0_AXI_BUSMON_CHN10_DN_RLATENCY  (PUB0_AXI_BUSMON10_BASE+0xC)
#define PUB0_AXI_BUSMON_CHN10_DN_WLATENCY  (PUB0_AXI_BUSMON10_BASE+0x14)
#define PUB0_AXI_BUSMON_CHN10_UP_RLATENCY  (PUB0_AXI_BUSMON10_BASE+0x1C)
#define PUB0_AXI_BUSMON_CHN10_UP_WLATENCY  (PUB0_AXI_BUSMON10_BASE+0x24)


#define PUB0_AXI_BUSMON_CHN_CFG(x) 		(x*0x10000+PUB0_AXI_BUSMON0_BASE+0x0)
#define PUB0_AXI_BUSMON_DN_RLATENCY(x)  (x*0x10000+PUB0_AXI_BUSMON0_BASE+0xC)
#define PUB0_AXI_BUSMON_DN_WLATENCY(x)  (x*0x10000+PUB0_AXI_BUSMON0_BASE+0x14)
#define PUB0_AXI_BUSMON_UP_RLATENCY(x)  (x*0x10000+PUB0_AXI_BUSMON0_BASE+0x1C)
#define PUB0_AXI_BUSMON_UP_WLATENCY(x)  (x*0x10000+PUB0_AXI_BUSMON0_BASE+0x24)

#define PUB1_AXI_BUSMON_CHN_CFG(x) 		(x*0x10000+PUB1_AXI_BUSMON0_BASE+0x0)
#define PUB1_AXI_BUSMON_DN_RLATENCY(x)  (x*0x10000+PUB1_AXI_BUSMON0_BASE+0xC)
#define PUB1_AXI_BUSMON_DN_WLATENCY(x)  (x*0x10000+PUB1_AXI_BUSMON0_BASE+0x14)
#define PUB1_AXI_BUSMON_UP_RLATENCY(x)  (x*0x10000+PUB1_AXI_BUSMON0_BASE+0x1C)
#define PUB1_AXI_BUSMON_UP_WLATENCY(x)  (x*0x10000+PUB1_AXI_BUSMON0_BASE+0x24)



#define IS_LPDDR4(x)    (((x&0xff000000) == 0x40000000)?TRUE:FALSE)
#define IS_LPDDR3(x)    (((x&0xff000000) == 0x30000000)?TRUE:FALSE)
#define IS_LPDDR2(x)    (((x&0xff000000) == 0x20000000)?TRUE:FALSE)
#define IS_DDR3(x)      (((x&0xff000000) == 0x3F000000)?TRUE:FALSE)
#define IS_2CS(x)       (((x&0x00f00000) == 0x00200000)?TRUE:FALSE)
#define IS_16BIT(x)     (((x&0x00000FF0) == 0x00000160)?TRUE:FALSE)
//#define CANDS_DEF_SETTING

#define CLKDIV_1400MHZ	0x7
#define CLKDIV_934MHZ	0x13
#define CLKDIV_466MHZ	0x17
#define CLKDIV_460MHZ	0xF
#define CLKDIV_234MHZ	0x2f
#define CLKDIV_233MHZ	0x1f
#define CLKDIV_933MHZ	0x7
#define CLKDIV_622MHZ	0x13
#define CLKDIV_368MHZ	0x23
#define CLKDIV_311MHZ	0x17
#define CLKDIV_156MHZ	0x2f
#define CLKDIV_26MHZ	0x4

typedef enum
{
    //lpddr2
    //DRAM_LPDDR2             = 0x20000000,
    DRAM_LPDDR2_1CS_2G_X32  = 0x20102320,
    DRAM_LPDDR2_1CS_4G_X32  = 0x20104320,
    DRAM_LPDDR2_1CS_8G_X32  = 0x20108320,
    DRAM_LPDDR2_2CS_4G_X32  = 0x20204320,
    DRAM_LPDDR2_2CS_6G_X32  = 0x20206320,
    DRAM_LPDDR2_2CS_8G_X32  = 0x20208320,
    DRAM_LPDDR2_2CS_12G_X32 = 0x20212320,
    DRAM_LPDDR2_2CS_16G_X32 = 0x20216320,

    //lpddr3
    //DRAM_LPDDR3             = 0x30000000,
    DRAM_LPDDR3_1CS_4G_X32  = 0x30104320,
    DRAM_LPDDR3_1CS_6G_X32  = 0x30106320,
    DRAM_LPDDR3_1CS_8G_X32  = 0x30108320,
    DRAM_LPDDR3_1CS_8G_X16X2= 0x30108162,
    DRAM_LPDDR3_1CS_12G_X32 = 0x30112320,
    DRAM_LPDDR3_1CS_16G_X32 = 0x30116320,
    DRAM_LPDDR3_2CS_8G_X32  = 0x30208320,
    DRAM_LPDDR3_2CS_12G_X32 = 0x30212320,
    DRAM_LPDDR3_2CS_16G_X32 = 0x30216320,
    DRAM_LPDDR3_2CS_16G_X32_X16X4 = 0x30216324,
    DRAM_LPDDR3_2CS_24G_X32_X16X4 = 0x30224324,
    DRAM_LPDDR3_2CS_24G_X32 = 0x30224320,
    DRAM_LPDDR3_2CS_32G_X32 = 0x30232320,

    //lpddr4
    //DRAM_LPDDR4             = 0x40000000,
    DRAM_LPDDR4_1CS_4G_X32  = 0x40104324,
    DRAM_LPDDR4_1CS_6G_X32  = 0x40106324,
    DRAM_LPDDR4_1CS_8G_X32  = 0x40108324,
    DRAM_LPDDR4_1CS_12G_X32 = 0x40112324,
    DRAM_LPDDR4_1CS_16G_X32 = 0x40116324,
    DRAM_LPDDR4_1CS_12G_X16 = 0x40112164,
    DRAM_LPDDR4_1CS_6G_X16  = 0x40106164,
    DRAM_LPDDR4_2CS_8G_X32  = 0x40208324,
    DRAM_LPDDR4_2CS_12G_X32 = 0x40212324,
    DRAM_LPDDR4_2CS_16G_X32 = 0x40216324,
    DRAM_LPDDR4_2CS_24G_X32 = 0x40224324,
    DRAM_LPDDR4_2CS_12G_X16 = 0x40212164,
    DRAM_LPDDR4_2CS_32G_X32 = 0x40232324,

    //ddr3
    //DRAM_DDR3               = 0x3f000000,
    DRAM_DDR3_1CS_2G_X8_4P  = 0x3f102084, //4-piece 2g bit ddr3 chips, 4 cs bonded into 1 cs, 8g bit together
    DRAM_DDR3_1CS_4G_X8_4P  = 0x3f104084, //4-piece 4g bit ddr3 chips, 4 cs bonded into 1 cs, 16g bit together
    DRAM_DDR3_1CS_8G_X8_4P  = 0x3f108084, //4-piece 8g bit ddr3 chips, 4 cs bonded into 1 cs, 32g bit together
    DRAM_DDR3_1CS_1G_X16_2P = 0x3f101162,
    DRAM_DDR3_1CS_2G_X16_2P = 0x3f102162, //2-piece 2g bit ddr3 chips, 2 cs bonded into 1 cs, 4g bit together
    DRAM_DDR3_1CS_4G_X16_2P = 0x3f104162, //2-piece 4g bit ddr3 chips, 2 cs bonded into 1 cs, 8g bit together
    DRAM_DDR3_1CS_8G_X16_2P = 0x3f108162, //2-piece 8g bit ddr3 chips, 2 cs bonded into 1 cs, 16g bit together
}DRAM_TYPE_E;


#ifdef DDR_AUTO_DETECT

typedef enum
{
	S16_SDRAM = 0,
}LP4_DDR_TYPE_E;

typedef enum
{
	LP4_MR8_SIZE_4Gb  =  0,
	LP4_MR8_SIZE_6Gb  =  1,
	LP4_MR8_SIZE_8Gb  =  2,
	LP4_MR8_SIZE_12Gb =  3,
	LP4_MR8_SIZE_24Gb =  4,
	LP4_MR8_SIZE_16Gb =  5,
	LP4_MR8_SIZE_32Gb =  6,
}LP4_MR8_DDR_SIZE_E;

typedef enum
{
	LP4_WIDTH_X16 = 0,
}LPDDR4_WIDTH_E;

typedef enum
{
	S4_SDRAM = 0,
	S2_SDRAM = 1,
	N_NVM = 2,
	S8_SDRAM = 3
}DDR_TYPE_E;

typedef enum
{
	MR8_SIZE_64Mb = 0,
	MR8_SIZE_128Mb = 1,
	MR8_SIZE_256Mb = 2,
	MR8_SIZE_512Mb = 3,
	MR8_SIZE_1Gb  =  4,
	MR8_SIZE_2Gb  =  5,
	MR8_SIZE_4Gb  =  6,
	MR8_SIZE_8Gb  =  7,
	MR8_SIZE_16Gb =  8,
	MR8_SIZE_32Gb =  9,

	MR8_SIZE_6Gb  =  14,
	MR8_SIZE_12Gb =  13
}MR8_DDR_SIZE_E;

typedef enum
{
	WIDTH_X32 = 0,
	WIDTH_X16 = 1,
	WIDTH_X8 = 2
}DDR_WIDTH_E;

struct MR8_size_info
{
	uint32 mr8_size;
	uint32 mem_size;
};

struct ddr_detect_info
{
	uint32 mem_size;
	uint32 mem_width;
	uint32 mem_type;
};
#endif


typedef enum
{
	PAD_DRV_HZ = 0x0,
	PAD_DRV_240 = 0x1,
	PAD_DRV_120 = 0x3,
	PAD_DRV_80 = 0x5,
	PAD_DRV_60 = 0x7,
	PAD_DRV_48 = 0xd,
	PAD_DRV_40 = 0xf,
	PAD_DRV_34 = 0xf,
	PAD_DRV_60_LP4 = 0x6,
	PAD_DRV_48_LP4 = 0x7,
}DDR_DS_E;

typedef enum
{
	PHY_SLICE0 = 0,
	PHY_SLICE1 = 1,
	PHY_SLICE2 = 2,
	PHY_SLICE3 = 3,
	PHY_SLICE4 = 4,
	PHY_CORE = 5,
}CANDS_PHY_SLICE_E;
typedef enum
{
	DDR_CHANNEL_0 = 0,
	DDR_CHANNEL_1 = 1,
}DDR_CHANNEL_NUM_E;



//*****************user define**********
//#define DDR_CLK_FLOATING
#define CODE_SIZE_OPTIMIZE
#define DRAM_TIMING_COSTDOWN



#ifdef DRAM_LPDDR3

#define DDR_CLK_CAL 233

#define TIMING_SET_SUM 4

#define FN_CTL_BOOT		0
#define FN_CTL_TARGET   0
#define FN_PI_TARGET    0 //should equal to map ctl fn!!!!

#define DO_DFS_INIT 1

#define F0_FREQ 233
#define F1_FREQ 368
#define F2_FREQ 622
#define F3_FREQ 933
#define F4_FREQ 233

//DBI
#define RD_DBI_EN	0
#define WR_DBI_EN	0


//should modify when lpddr4, stop fsp not equal to boot fsp, ie: f0(fsp0) -> f1 (fsp1) -> f2(fsp0) -> f3(fsp1), f0(fsp0)!=f3(fsp1),wr&op=1
#define FSP_WR 0
#define FSP_OP 0
//#define PHY_PLL_BYPASS
#else

#define DDR_CLK_CAL 26

#define TIMING_SET_SUM 5

#define FN_CTL_BOOT	4
#define FN_CTL_TARGET   3
#define FN_PI_TARGET    FN_CTL_TARGET+1 //should equal to map ctl fn!!!!

#define DO_DFS_INIT 1

#define F0_FREQ 234 
#define F1_FREQ 466
#define F2_FREQ 934
#define F3_FREQ 1400
#define F4_FREQ 26

//DBI
#define RD_DBI_EN	0
#define WR_DBI_EN	0


//should modify when lpddr4, stop fsp not equal to boot fsp, ie: f0(fsp0) -> f1 (fsp1) -> f2(fsp0) -> f3(fsp1), f0(fsp0)!=f3(fsp1),wr&op=1
#define FSP_WR 1
#define FSP_OP 1
//#define PHY_PLL_BYPASS
#endif

#define LP4_BOOT_LOW_FREQ 1
#define PHY_LOW_FREQ_SEL_F0	1
#define PHY_LOW_FREQ_SEL_F1	1
#define PHY_LOW_FREQ_SEL_F2	0
#define PHY_LOW_FREQ_SEL_F3	0

#ifdef DRAM_LPDDR3
//training
//--------- pi
#define PI_F0_TRAIN 1
#define PI_F1_TRAIN 1
#define PI_F2_TRAIN 1
#define PI_F3_TRAIN 1
#define PI_F4_TRAIN 1

#define PI_INITLVL_EN 1
#define PI_NORMAL_LVL_EN 1
#define PI_START 1
#define PI_DFS_PERDIC_LVL_EN_LP3 0
#define PI_SRE_PERDIC_LVL_EN_LP3 0
#define PI_DFS_PERDIC_LVL_EN_LP4 0
#define PI_SRE_PERDIC_LVL_EN_LP4 0

#define PI_RDLVL_EN_INIT	 0
#define PI_RDLVL_EN_NOINIT	 1
#define PI_RDLVL_GATE_EN_INIT	1
#define PI_RDLVL_GATE_EN_NOINIT	1
#define PI_RD_PREAMBLE_TR_EN	0
#define PI_RDLVL_PERDIC_EN	0
#define PI_RDLVL_SRE_EN	0
#define PI_RDLVL_GATE_PERDIC_EN	0
#define PI_RDLVL_GATE_SRE_EN	0

#define PI_WRLVL_EN_INIT	 0
#define PI_WRLVL_EN_NOINIT	 1
#define PI_WRLVL_PERDIC_EN	 0
#define PI_WRLVL_SRE_EN	 0

#define PI_CALVL_EN_INIT	 0
#define PI_CALVL_EN_NOINIT	 1
#define PI_CALVL_PERDIC_EN	 0
#define PI_CALVL_SRE_EN	 0
#define PI_CALVL_VREF_EN   0

#define PI_WDQLVL_EN_INIT	0
#define PI_WDQLVL_EN_NOINIT	0
#define PI_WDQLVL_PERDIC_EN	0
#define PI_WDQLVL_SRE_EN	0
#define PI_WDQLVL_VREF_EN 0

#else

//training
//--------- pi
#define PI_F0_TRAIN 0
#define PI_F1_TRAIN 0
#define PI_F2_TRAIN 1
#define PI_F3_TRAIN 1
#define PI_F4_TRAIN 1 

#define PI_INITLVL_EN 1
#define PI_NORMAL_LVL_EN 1
#define PI_START 1
#define PI_DFS_PERDIC_LVL_EN_LP3 0
#define PI_SRE_PERDIC_LVL_EN_LP3 0
#define PI_DFS_PERDIC_LVL_EN_LP4 0
#define PI_SRE_PERDIC_LVL_EN_LP4 0

#define PI_RDLVL_EN_INIT	1
#define PI_RDLVL_EN_NOINIT	0
#define PI_RDLVL_GATE_EN_INIT	1
#define PI_RDLVL_GATE_EN_NOINIT	0
#define PI_RD_PREAMBLE_TR_EN	1
#define PI_RDLVL_PERDIC_EN	0
#define PI_RDLVL_SRE_EN		0
#define PI_RDLVL_GATE_PERDIC_EN	0
#define PI_RDLVL_GATE_SRE_EN	0

#define PI_WRLVL_EN_INIT	1
#define PI_WRLVL_EN_NOINIT	0
#define PI_WRLVL_PERDIC_EN	0
#define PI_WRLVL_SRE_EN		0

#define PI_CALVL_EN_INIT	1
#define PI_CALVL_EN_NOINIT	0
#define PI_CALVL_PERDIC_EN	0
#define PI_CALVL_SRE_EN		0
#define PI_CALVL_VREF_EN 	1

#define PI_WDQLVL_EN_INIT	1
#define PI_WDQLVL_EN_NOINIT	0
#define PI_WDQLVL_PERDIC_EN	0
#define PI_WDQLVL_SRE_EN	0
#define PI_WDQLVL_VREF_EN 	1

#endif

//--------- ctl
//init training
#define CALVL_EN  0
#define WRLVL_EN  0
#define RDGLVL_EN 0
#define RDELVL_EN 0
#define ZQ_EN     0
#define RD_PREAMBLE_TR_EN 0
//dfs exit trainig
#define CALVL_EN_DFS  0
#define WRLVL_EN_DFS  0
#define RDGLVL_EN_DFS 0
#define RDELVL_EN_DFS 0
#ifdef DRAM_LPDDR3
#define ZQ_EN_DFS     1
#else
#define ZQ_EN_DFS     1
#endif
//self-refresh exit traing
#define CALVL_EN_SREF  0
#define WRLVL_EN_SREF  0
#define RDGLVL_EN_SREF 0
#define RDELVL_EN_SREF 0
#define ZQ_EN_SREF     0


//--------- PHY
#ifdef DRAM_LPDDR3
#define PHY_CSLVL_EN	0 //cs training during ca training
#define PHY_ADDR_SLEW_RATE	7
#define PHY_CKE_SLEW_RATE	7
#define PHY_CLK_SLEW_RATE	7
#define PHY_CS_SLEW_RATE	7
#define PHY_DATA_SLEW_RATE	7
#define PHY_DQS_SLEW_RATE	7
#define PHY_FDBK_SLEW_RATE	7
#define PHY_RST_SLEW_RATE	7

#define PHY_ADDR_DRV	PAD_DRV_40
#define PHY_CKE_DRV	PAD_DRV_40
#define PHY_CLK_DRV	PAD_DRV_40
#define PHY_CS_DRV	PAD_DRV_40
#define PHY_DATA_DRV	PAD_DRV_40
#define PHY_DQS_DRV	PAD_DRV_40
#define PHY_FDBK_DRV	PAD_DRV_40
#define PHY_RST_DRV	PAD_DRV_40

//ODT
#define PHY_DQDQS_ODT_RD_EN	0
#define PHY_DQDQS_ODT_WR_EN	0
#define PHY_DQDQS_ODT_IDLE_EN	0

#define PHY_ADR_ODT_EN   0
#define PHY_CKE_ODT_EN   0
#define PHY_CLK_ODT_EN   0
#define PHY_CS_ODT_EN    0
#define PHY_DQS_ODT_EN   0
#define PHY_DFBK_ODT_EN  0
#define PHY_RST_ODT_EN   0


#define PHY_DQDQS_ODT_RD_DRV_P	PAD_DRV_120
#define PHY_DQDQS_ODT_RD_DRV_N	PAD_DRV_120
#define PHY_DQDQS_ODT_WR_DRV	PHY_DATA_DRV
#define PHY_DQDQS_ODT_IDLE_DRV 	PAD_DRV_HZ
#define PHY_ADR_ODT_DRV 	PHY_ADDR_DRV
#else

#define PHY_CSLVL_EN	1 //cs training during ca training
#define PHY_ADDR_SLEW_RATE	7
#define PHY_CKE_SLEW_RATE	7
#define PHY_CLK_SLEW_RATE	7
#define PHY_CS_SLEW_RATE	7
#define PHY_DATA_SLEW_RATE	7
#define PHY_DQS_SLEW_RATE	7
#define PHY_FDBK_SLEW_RATE	7
#define PHY_RST_SLEW_RATE	7

#define PHY_ADDR_DRV	PAD_DRV_48_LP4
#define PHY_CKE_DRV	PAD_DRV_48_LP4
#define PHY_CLK_DRV	PAD_DRV_48_LP4
#define PHY_CS_DRV	PAD_DRV_48_LP4
#define PHY_DATA_DRV	PAD_DRV_60_LP4
#define PHY_DQS_DRV	PAD_DRV_60_LP4
#define PHY_FDBK_DRV	PAD_DRV_48_LP4
#define PHY_RST_DRV	PAD_DRV_48_LP4

//ODT
#define PHY_DQDQS_ODT_RD_EN	1
#define PHY_DQDQS_ODT_WR_EN	1
#define PHY_DQDQS_ODT_IDLE_EN	0

#define PHY_ADR_ODT_EN   0
#define PHY_CKE_ODT_EN   0
#define PHY_CLK_ODT_EN   0
#define PHY_CS_ODT_EN    0
#define PHY_DQS_ODT_EN   0
#define PHY_DFBK_ODT_EN  0
#define PHY_RST_ODT_EN   0


#define PHY_DQDQS_ODT_RD_DRV_P	PAD_DRV_HZ
#define PHY_DQDQS_ODT_RD_DRV_N	PAD_DRV_60_LP4
#define PHY_DQDQS_ODT_WR_DRV	PAD_DRV_60_LP4
#define PHY_DQDQS_ODT_IDLE_DRV 	PAD_DRV_HZ
#define PHY_ADR_ODT_DRV 	PAD_DRV_48_LP4
#endif
#define PHY_IE_ALWAYS_ON 0
//#define POWER_TEST
#ifdef POWER_TEST
void ddr_power_test(void);
#endif
//**************************************
